The present invention relates to a nonvolatile semiconductor memory device and a semiconductor integrated circuit.
In various kinds of memory devices for portable units and various kinds of memory-incorporated logic VLSI's, the technologies for nonvolatile memory devices have recently become increasingly important because it is an urgent task to reduce the costs per bit, while further enhancing the electrical write functions thereof. In order to develop such a high-performance device with a reduced cost, various structures and fabrication processes have been suggested.
Hereinafter, examples of conventional nonvolatile semiconductor memory devices will be described.
FIG. 18 shows the cross section of a nonvolatile semiconductor memory device having a so-called "stack-type" structure. Such a structure was suggested by S. Mukherjee, et al. in IEEE IEDEM 1985, Technical Digest, p. 616.
In the device shown in FIG. 18, a tunnel oxide film 102, a floating gate 103, a capacitive insulating film 104 and a control gate 105 are stacked in this order on a semiconductor substrate 101. In the surface of the semiconductor substrate 101, a source region 106 and a drain region 107, which have been doped with an impurity having a high concentration, are formed. The region between the source region 106 and the drain region 107 functions as a channel region. The floating gate 103 is formed so as to overlap the channel region. This nonvolatile semiconductor memory device has a "stacked gate structure" in which the control gate 105 is disposed over the floating gate 103 which is covered with oxide films in the periphery thereof. The floating gate 103 functions as a node in which information is stored and the stored information is variable between "0" and "1" depending upon the charged states thereof. The threshold voltage of a transistor as viewed from the control gate 105 is varied in accordance with the amount of charge accumulated in the floating gate 103. By utilizing this phenomenon, the read of data is performed. On the other hand, the write of data is performed by utilizing the phenomenon that channel hot electrons, which have obtained high energy as a result of the acceleration caused by a high electric field in a lateral direction within an inversion layer of the channel, are injected into the tunnel oxide film 102 so as to reach the floating gate 103. As will be described later, the efficiency with which the electrons, which have obtained high energy as a result of the acceleration caused by the high electric field in the lateral direction within the inversion layer of the channel, are injected into the tunnel oxide film 102 is extremely low. Thus, the write efficiency is also low. The high channel doping concentration is required to improve the write efficiency, resulting in the high threshold voltage and read current. The erasure of data is performed by taking out the electrons in the floating gate 103 into the source region 106 in accordance with a Fowler-Nordheim (FN) tunneling phenomenon. In order to utilize the FN tunneling phenomenon, a high electric field of about 10.5 V/cm to about 11 V/cm is required to be formed in the tunnel oxide film 102. Thus, when data is erased, the control gate 105 is grounded (0 V) and a high voltage of about 15 V is applied to the source region 106, for example.
FIG. 19 shows the cross section of a nonvolatile semiconductor memory device, which has been suggested in order to suppress the degradation in cell operation margin when data is erased. Such a device is disclosed by H. Kume, et al. in IEEE IEDEM 1987, Technical Digest, p. 560.
In the device shown in FIG. 19, a tunnel oxide film 202, a floating gate 203, a capacitive insulating film 204 and a control gate 205 are stacked in this order on a semiconductor substrate 201. In the surface of the semiconductor substrate 201, a high-concentration source region 206 and a high-concentration drain region 207, which have been doped with an impurity having a high concentration, are formed. In addition, an n.sup.- type low-concentration impurity layer 208 and a p.sup.+ -type high-concentration impurity layer 209 are formed so as to cover the n.sup.+ -type high-concentration source region 206 and the n.sup.+ -type high-concentration drain region 207, respectively. The region between the n-type low-concentration impurity layer 208 and the n.sup.+ -type high-concentration drain region 207 functions as a channel region. The floating gate 203 is formed so as to overlap the channel region and the ends of the floating gate 203 overlap a part of the high-concentration source region 206 and a part of the high-concentration drain region 207, respectively.
This device has an electric field weakening source structure. Thus, in erasing data, it is possible to suppress the generation of electrons and holes resulting from band-to-band tunneling current in the vicinity of the channel region, thereby reducing the amount of holes injected into the tunnel oxide film 202. As a result, it is possible to prevent the holes from being trapped in the tunnel oxide film 202 and it is also possible to prevent interface states from being generated, thereby reducing a variation in erasure characteristics and preventing a degradation of a retention margin and a write disturb margin.
FIG. 20 shows the cross section of a nonvolatile semiconductor memory device, which is designed to shorten a write time or to reduce a write voltage by increasing a write efficiency. This device is disclosed by Nakao, et al. in Japanese Laid-Open Publication No. 7-115142.
The device shown in FIG. 20 uses a semiconductor substrate 301 with a step 302 formed on the surface thereof. The surface of the semiconductor substrate 301 is divided by this step 302 into a surface region at a relatively high level (first surface region) and a surface region at a relatively low level (second surface region). A tunnel oxide film 303, a floating gate 304, a capacitive insulating film 305 and a control gate 306 are stacked in this order over the step 302. In the surface of the semiconductor substrate 301, a high-concentration source region 307 and a high-concentration drain region 308, which have been doped with an impurity having a high concentration, are formed. A high-concentration impurity layer 309 having a small thickness of about 0.1 .mu.m or less extends from the high-concentration drain region 308 along the side of the step 302 to reach the first surface region. Since the high-concentration impurity layer 309 functions as a drain region, a region between the high-concentration source region 307 and the high-concentration impurity layer 309 functions as a channel region. The floating gate 304 is formed so as to overlap the channel region and to cover the high-concentration impurity layer 309.
In such a structure, since the floating gate 304 is located in the directions of velocity vectors of channel hot electrons, the channel hot electron injection efficiency is presumably increased.
Next, a method for fabricating the nonvolatile semiconductor memory device shown in FIG. 20 will be described with reference to FIGS. 21A to 21E.
First, as shown in FIG. 21A, an oxide film 311 is formed as a mask for forming a step in the semiconductor substrate 301 made of p-type silicon. Thereafter, a part of the oxide film 311 in the region where the step is to be formed is etched by a commonly used patterning technique. Then, the semiconductor substrate 301 is etched by using the oxide film 311 as a mask, thereby forming a step in the surface of the semiconductor substrate 301. Subsequently, arsenic (As) ions are implanted into the whole of the step side region and the second surface region at a relatively high dose of about 1.0.times.10.sup.15 cm.sup.-2 and with an acceleration energy of about 20 keV. This ion implantation is performed by a large-angle-tilt ion implantation technique in which the implantation angle is set at about 30 degrees. As a result, as shown in FIG. 21B, the high-concentration impurity layer 309 having a small thickness is formed in the whole of the step side region and the second surface region. As described in the above-cited document, the high-concentration impurity layer 309 thermally diffuses during the fabrication process and the resulting thickness thereof, after the fabrication process is completed, becomes about 0.05 .mu.m. Next, as shown in FIG. 21C, the oxide film 311 is removed and then the surface of the semiconductor substrate 301 is thermally oxidized, thereby forming the tunnel oxide film 303 as a first insulating film having a thickness of about 10 nm. Furthermore, a CVD poly-silicon film having a thickness of about 200 nm is deposited thereon, thereby forming the floating gate 304. A second insulating film 305 (thickness: about 20 nm) functioning as a capacitive insulating film is formed on the floating gate 304 by thermally oxidizing the surface of the floating gate 304. Thereafter, another CVD poly-silicon film having a thickness of about 200 nm is deposited thereon, thereby forming the control gate 306.
Subsequently, the floating gate 304, the capacitive insulating film 305 and the control gate 306 are patterned as shown in FIG. 21D. Finally, as shown in FIG. 21E, As ions are implanted into the. semiconductor substrate 301 at a dose of about 3.0.times.10.sup.15 cm.sup.-2 and with an acceleration energy of about 50 keV, thereby forming the high-concentration source region 307 and the high-concentration drain region 308.
The conventional nonvolatile semiconductor memory devices have the following problems.
In the structure shown in FIG. 18, the conditions for making electrons obtain high energy do not match with the conditions for efficiently injecting electrons into the oxide film. As a result, the injection efficiency (i.e., the ratio of injected current to consumed power) becomes as low as about 10.sup.-6. Thus, a large amount of data cannot be written in parallel into such a structure in the case of performing a page mode write operation, for example, and the resulting data transfer rate becomes low. The time required for such a device to rewrite data is about 10 .mu.s, which is extremely longer than the rewrite time required for a DRAM, an SRAM or the like.
Since the structures shown in FIGS. 18 and 19 utilize the FN tunneling phenomenon for erasing data, an abrupt band bending and a high electric field are generated at the edge of the source region in the vicinity of the surface thereof. The abrupt band bending and the high electric field in turn cause band-to-band tunneling current, so that the generated holes are injected into the oxide film. As a result, a variation is adversely caused in erasure characteristics and a retention margin and a write disturb margin are degraded. Particularly when a large amount of data is simultaneously erased from a large number of nonvolatile memory cells included within a large block, it takes a time 100 times or more as long as the time required for one-bit erasure. Thus, in a memory cell having a weak resistance, the retention margin is seriously degraded.
In the structure shown in FIG. 19, the variation in erasure characteristics and the degradation of a retention margin and a write disturb margin can be suppressed. However, since the structure uses a low-concentration source diffusion layer, the effective channel length thereof is decreased, which makes it impossible to greatly reduce the size of a cell. In addition, even when the drain voltage is restricted to about 1.5 V during the read of data, it is still impossible to suppress the read disturb margin from being degraded.
Furthermore, none of the above-described conventional examples can employ a circuit configuration for erasing data by taking out electrons from a floating gate into a drain region by utilizing the FN tunneling phenomenon. Such a circuit configuration is advantageous in stabilizing the sensing operation and realizing a high-speed access. However, it is necessary to weaken a drain electric field in order to suppress the generation of band-to-band tunneling current during an erasure operation. Weakening the drain electric field considerably decreases the electron injection efficiency during a write operation.
In the nonvolatile semiconductor memory device shown in FIG. 20, since the floating gate 304 is formed in the directions of the velocity vectors of channel hot electrons, the channel hot electron injection efficiency is allegedly increased. For such a purpose, a thin drain layer 309 is formed as a high-concentration impurity layer having a symmetric impurity concentration so as to uniformly cover the side of the step by implanting As ions by a large-angle-tilt ion implantation in which the implantation angle is set at about 30 degrees, the acceleration energy is set at as low as about 20 keV and the dose is set at about 1.0.times.10.sup.15 cm.sup.-2. The resulting impurity concentration of the high-concentration impurity layer 309 becomes as high as about 1.0.times.10.sup.20 cm.sup.-3.
However, in the structure shown in FIG. 20 in which the high-concentration drain layer 309 reaches the surface in the upper part of the step, the electron injection efficiency cannot be increased and the variation in erasure characteristics and the degradation of the write disturb margin and the read disturb margin cannot be suppressed. The reasons thereof are as follows. At the edge of the high-concentration drain layer 309, a drain potential, which has been applied to the drain region in a corner portion in the upper part of the step, can be retained. However, the electric field intensity in the horizontal direction dramatically decreases in the high-concentration drain layer 309 and the energy of hot electrons decreases in the interface between the step side region and the semiconductor substrate. Though some distance is generated by the non-equilibrium transportation of the electrons between the position of the peak of electric field and the position of an average energy peak of electrons, the distance is approximately on the order of a mean free path. In a silicon crystal, the difference is about 10 nm. As the difference between the set thickness of the thin drain layer and this distance increases, the energy of electrons in the silicon interface in the step side region exponentially decreases so that the electron injection efficiency is decreased. That is to say, this structure requires a drain layer having an extremely small thickness. Furthermore, in the high-concentration drain layer, a larger number of hot electrons come into contact with the electrons in a thermal equilibrium state, thereby scattering the electrons, making the directions of the electron velocity vectors less aligned with the direction of the electric field and decreasing the electron injection efficiency. Thus, for example, if the impurity concentration within the drain layer is symmetrically decreased so as to suppress the scattering of electrons within the drain layer, then the drain potential drops in the extremely thin drain layer formed along the side and the bottom of the step, the drain potential also drops in the corner portion in the upper part of the step and the electric field intensity decreases in the horizontal direction between the drain layer and the channel. As a result, the electron injection efficiency also decreases in the step side region.
Moreover, in this structure, it is also impossible to erase data by taking out electrons from the floating gate into the drain layer by utilizing the FN tunneling phenomenon. Since the high-concentration drain layer is in contact with the channel region, it is necessary to form an electric field weakening diffusion layer, for example, around the high-concentration drain region in order to suppress the generation of the band-to-band tunneling current during an erasure operation. However, in such a case, the electron injection efficiency is extremely decreased during a write operation, and such a structure cannot be fabricated at a very small size because of a short channel effect.
Furthermore, even when the drain voltage is restricted to about 1.5 V during a read operation, the read disturb margin is degraded by the thin high-concentration drain layer.